1. Field of the Invention
The present invention relates generally to voltage supply circuits, and more specifically, to a voltage supply circuit built in a semiconductor device.
2. Description of the Background Art
As the integration density of dynamic semiconductor memory devices increased, the gate oxide films of transistors have become thin, and therefore supplying external power supply voltage directly to internal circuits should be avoided in view of reliability. Besides, if an internal circuit is directly driven by external power supply voltage, power consumption increases. For these reasons, 16M bit DRAMs (Dynamic Random Access Memories) have a built-in internal down converter for down-converting external power supply voltage in a chip for supply to an internal circuit.
Such an internal down converter permits electric field to be applied to the gate oxide film of a transistor to be relaxed, thereby increasing reliability. The discharge current of the internal circuit is reduced by the decrease of the power supply voltage and power consumption is reduced.
FIG. 8 is a circuit diagram showing the structure of a conventional internal down converter.
The internal down converter shown in FIG. 8 includes a reference voltage generation circuit 10, a differential amplification circuit 20, a driver circuit 30 and a level shifter circuit 40.
Reference voltage generation circuit 10 includes P channel MOS transistors 101-107. Transistors 101, 102, and 103 are connected in series between a power supply line L1 receiving an external power supply voltage Vext and a ground line receiving a ground potential. Each of transistors 101, 102, and 103 are diode-connected. Transistors 104, 105, 106, and 107 are also connected in series between power supply line L1 and the ground line. Each of transistor 104, 105, 106, and 107 are also diode-connected. The gate of transistor 104 is connected to a node N1 between transistors 102 and 103.
Transistor 103 has a large impedance and a voltage (Vext-2 Vtp) is output to node N1. Herein, Vtp is a threshold voltage for a P channel MOS transistor. The potential difference between the gate and source of transistor 104 becomes 2 Vtp irrespective of the external power supply voltage Vext. Accordingly, transistor 104 operates as a constant current source.
Therefore, a reference voltage Vref is output to a node N2 between transistors 104 and 105 by combining the constant current source and diode-connected transistors 105, 106, and 107. The reference voltage Vref is equal to 3 Vtp.
Differential amplification circuit 20 includes P channel MOS transistors 201, 202, 203 and N channel MOS transistors 204, 205, 206. Transistors 202, 203, 204 and 205 constitute a current mirror circuit. The reference voltage Vref is applied to the gate of transistor 204 from reference voltage generation circuit 10, while the output voltage of level shifter circuit 40 is applied to the gate of transistor 205.
Transistor 201 is connected between power supply line L1 and a node N3. Transistor 206 is connected between a node N4 and the ground line. A control signal VDCE is applied to the gates of transistors 201 and 206.
When the control signal VDCE is in an "H" level, differential amplification circuit 20 is activated. Differential amplification circuit 20 compares the output voltage of level shifter circuit 40 to the reference voltage Vref from reference voltage generation circuit 10 and outputs a signal of an "H" or "L" level to node N3. When the output voltage of level shifter circuit 40 is lower than the reference voltage Vref from reference voltage generation circuit 10, a signal of "L" level is output to node N3. If the output voltage of level shifter circuit 40 is higher than the reference voltage Vref from reference voltage generation circuit 10, a signal of "H" level is output to node N3.
When the control signal VDCE is in an "L" level, differential amplification circuit 20 is deactivated. In this case, transistor 201 is turned on, and node N3 is charged to "H".
Driver circuit 30 includes a P channel MOS transistor 301. Transistor 301 is connected between power supply line L1 and a power supply line L5, with its gate being connected to the node N3 of differential amplification circuit 20.
Driver circuit 30 is activated when the output signal of differential amplification circuit 20 is in an "L" level, and deactivated when the output signal of differential amplification circuit 20 is in an "H" level. An internal voltage Vint is supplied to power supply line L5 by driver circuit 30.
Level shifter circuit 40 includes P channel MOS transistors 401 and 402. Transistors 401 and 402 are connected in series between power supply line L5 and the ground line.
A node N5 between transistors 401 and 402 is connected to the gate of transistor 205 in differential amplification circuit 20. A control signal /VDCE is applied to the gate of transistor 401. The control signal /VDCE is the inverse of the control signal VDCE. Transistor 402 is diode-connected.
Level shifter circuit 40 is activated when the control signal /VDCE is in an "L" level, and deactivated when the control signal /VDCE is in an "H" level. Level shifter circuit 40 resistance-divides the internal voltage Vint by the channel resistors R1 and R2 of transistors 401 and 402, and outputs the resistance-divided output voltage to node N5. The output voltage is decided by the ratio of channel resistors R1 and R2.
An operation of the internal down converter shown in FIG. 9 will be described by referring to the characteristics of the internal down converter shown in FIG. 8.
The reference voltage Vref (=3 Vtp) is generated by reference voltage generation circuit 10. Assuming that a threshold voltage Vtp for a P channel MOS transistor is 0.9V, the reference voltage Vref is 2.7V. The external power supply voltage Vext is, for example, 5V.
Level shifter circuit 40 is activated when the control signal /VDCE is in an "L" level. The ratio of channel resistors R1 and R2 of transistors 401 and 402 is so set that an output voltage 2.7/4 times as large as the internal voltage Vint is supplied to node N5. In this case, if the internal voltage Vint is 4V, the output voltage of node N5 is 2.7V.
Differential amplification circuit 20 is activated when the control signal VDCE is in an "H" level. Reference voltage generation circuit 10 compares the output voltage of node N5 of level shifter circuit 40 to the reference voltage Vref (=2.7V) from reference voltage generation circuit 10.
When the output voltage of node N5 is smaller than 2.7V, in other words when the internal voltage Vint is smaller than 4V, the signal of node N3 attains an "L" level. Thus, transistor 301 in driver circuit 30 is turned on, and power supply line L5 is charged with the external power supply voltage Vext. As a result, the internal voltage Vint increases.
When the output voltage of node N5 is larger than 2.7V, in other words when the internal voltage Vint is larger than 4V, the signal of node N3 attains an "H" level. Thus, transistor 301 in driver circuit 30 is turned off. As a result, supply of the external power supply voltage Vext to power supply line L5 stops.
By repeating the above-stated operation, if the external power supply voltage Vext is at least 4V, as illustrated in FIG. 9, the internal voltage Vint is held at 4V. If the external power supply voltage Vext is smaller than 4V, the internal voltage Vint is equal to the external power supply voltage Vext.
Meanwhile, in semiconductor manufacturing factories, various pre-shipment tests are conducted in order to find semiconductor devices with initial failures and prevent the faulty devices from being shipped. Burn-in test is commonly conducted as one of such tests before shipment, in which a test semiconductor device is operated under a power supply voltage higher than a designed usual power supply voltage and at a high ambient temperature for a long period of time.
For a semiconductor device such as DRAM, an external power supply voltage of 5.0V is supplied at an ambient temperature in the range from 0.degree. C. to 70.degree. C. in normal operation, and an external power supply voltage of 8.0V is supplied at an ambient temperature of 125.degree. C. in a burn-in test. An internal down-converter (or voltage supply circuit) taking into account such a burn-in test will be described in the following.
FIG. 10 is a block diagram showing an internal down converter taking into account a burn-in test. FIG. 10 illustrates the background of the present invention. Referring to FIG. 10, internal down converter 100 includes a reference voltage generation circuit for burn-in test 10a', a reference voltage generation circuit for usual. operation 10b', a voltage selection circuit 90, a differential amplification circuit 20, and a driver circuit 30.
Reference voltage generation circuits 10a' and 10b' are each supplied with an external power supply voltage (5.0V for example) Vext and generate a reference voltage Vrefb for burn-in test and a reference voltage Vrefn for normal operation, respectively. The reference voltages Vrefb and Vrefn are applied to voltage selection circuit 90. Voltage selection circuit 90 compares the applied voltages Vrefb and Vrefn and selectively applies the higher one of them as a reference voltage Vref to differential amplification circuit 20.
Differential amplification circuit 20 is activated in response to a control signal VDCE and performs a differential operation in response to the applied reference voltage Vref and an internal voltage (or internal cower supply voltage) Vint. Driver circuit 30 outputs the internal voltage Vint in response to a control voltage Vc output from differential amplification circuit 20. The output voltage Vint is supplied as an internal power supply voltage to an internal circuit (not shown) and is also applied to differential amplification circuit 20.
FIG. 11 is a representation showing voltage characteristics for use in illustration of the relation between the external power supply voltage Vext and the reference voltage Vref selected by voltage selection circuit 90 shown in FIG. 10. Referring to FIG. 11, the abscissa represents the external power supply voltage Vext (V), while the ordinate represents the reference voltage Vref (V). In FIG. 11, the polygonal line (or curve) in solid line represents the voltage selected by selection circuit 90 shown in FIG. 10, in other words represents the reference voltage Vref applied to differential amplification circuit 20.
In FIG. 11, straight line 251 represents a relation Vref=Vext, straight line 252 Vref=3.3V (constant), and straight line 253 represents Vref=Vext-2.7V.
When the external power supply voltage Vext&lt;3.3V, the reference voltage Vref equal to the external power supply voltage Vext is output. Accordingly, in this range, the reference voltage Vref is present on straight line 251.
Voltage selection circuit 90 shown in FIG. 10 selectively outputs the higher one of the applied two voltages Vrefb and Vrefn. Therefore, when 3.3.ltoreq.Vext.ltoreq.6.0 (V), a predetermined voltage of 3.3V is output as the reference voltage Vref.
Differential amplification circuit 20 shown in FIG. 10 controls driver circuit 30 to make the internal voltage Vint equal to the reference voltage Vref, in response to the internal voltage or internal power supply voltage Vint and the applied reference voltage Vref. Driver circuit 30 controls the level of the internal voltage Vint in response to the control voltage Vc applied from differential amplification circuit 20.
Accordingly, when 3.3V.ltoreq.Vext.ltoreq.6.0V as illustrated in FIG. 11, since the reference voltage Vref of 3.3V (constant) is applied to differential amplification circuit 20, in this range, the voltage Vint of 3.3V (constant) is supplied as the internal power supply voltage to the internal circuit (not shown).
When, for example, a certain semiconductor device operates in a normal operation mode, an external power supply voltage Vext of 5.0V is applied, and its internal down converter 100 supplies a voltage Vint of 3.3V (constant) as an internal power supply voltage to the internal circuit.
As described above, a circuit configuration for burn-in test should be taken into account in a semiconductor device. For example, internal down converter 100 shown in FIG. 10 has a special characteristic for burn-in test shown in FIG. 11. Referring back to FIG. 11, when an external power supply voltage Vext of 8.0V is supplied, voltage selection circuit 90 shown in FIG. 10 outputs a reference voltage Vref of 5.3V (see point P10). More specifically, if the external power supply voltage Vext varies in the range represented by 6.0V&lt;Vext, the reference voltage Vref is present on straight line 253 representing Vref=Vext-2.7V. Stated differently, the characteristic shown in FIG. 11 is provided for the relation between voltage selection circuit 90, and reference voltage generation circuits 10a' and 10b' shown in FIG. 10, in order to satisfy the conditions (point P10) for the above-described burn-in test in the range of 6.0V&lt;Vext.
Accordingly, internal down converter 100 shown in FIG. 10 can supply the voltage Vint of 3.3V (constant) as the internal power supply voltage only when 3.3V.ltoreq.Vext.ltoreq.6.0V. Stated differently, when 6.0V&lt;Vext, the internal voltage Vint higher than 3.3V is output, and the following disadvantage is encountered in the internal circuit which is not shown.
Referring back to FIG. 8, the internal down converter operates at a high temperature (about in the range from 70.degree. C. to 80.degree. C.), the threshold voltage Vtp of the channel MOS transistor is reduced by about 0.07V compared to its operating at a room temperature (for example at 25.degree. C.). Therefore, the reference voltage Vref (=3 Vtp) decreases at the time of high temperature operation by about 0.21V as compared to at the time of room temperature operation. Accordingly, the reference voltage Vref is 2.49V when operating at a high temperature.
In this case, since differential amplification circuit 20 controls driver circuit 30 so that the output voltage of level shifter circuit 40 is equal to 2.49V, the internal voltage Vint becomes 2.49.multidot.(4/2.7)=3.69 [V] when operating at a high temperature. Thus, the internal voltage Vint decreases at the time of high temperature operation by significant 0.31V as compared to at the time of room temperature operation.
As a result, in a semiconductor memory device having an internal down converter as shown in FIG. 8 built therein, accessing speed is reduced by the decrease of the internal voltage Vint.
In a conventional internal down converter, when the reference voltage Vref generated by reference voltage generation circuit 10 changes in accordance with changes in parameters in a process, the internal voltage Vint supplied by driver circuit 30 changes as well. When the reference voltage Vref increases the internal voltage Vint increases, and when the reference voltage Vref decreases, the internal voltage Vint decreases as well.
For example, if the reference voltage Vref changes by 0.1V, the internal voltage Vint changes by the amount of 0.1.times.(4/2.7)=0.15 [V]. Thus, in the conventional internal down converter, an undesirable change in the internal voltage in accordance with a change in parameters in a process is encountered.
Meanwhile, as has already been pointed out about internal down converter 100 shown in FIG. 10, internal down converter 100 can supply a desired internal voltage Vint (=3.3V) to the internal circuit (not shown) only when 3.3V.ltoreq.Vext.ltoreq.6.0V as shown in FIG. 11. If an external power supply voltage Vext higher than 6.0V is supplied at an ambient temperature for normal operation, as can be seen from FIG. 11, a voltage Vint higher than 3.3V will be supplied to the internal circuit as the internal power supply voltage.
Generally, when a power supply voltage in excess of a designed power supply voltage level is supplied to a semiconductor integrated circuit, an erroneous operation timing is generated in the semiconductor integrated circuit. More specifically, when a power supply voltage having a higher level is supplied, transistors (including field effect transistors and bipolar transistors) forming the semiconductor integrated circuit operate faster than usual. This suggests that in some cases a designed operation timing in some circuit can not be obtained.
In order to avoid this problem, a designed internal power supply voltage of 3.3V (constant) should be supplied to the internal circuit (not shown), which necessitates the accepted range of the external power supply voltage Vext being 3.3V.ltoreq.Vext.ltoreq.6.0V. In other words, in order to satisfy the conditions for burn-in test (point P10 shown in FIG. 11), the range of the external power supply voltage Vext which can be supplied to internal down converter 100 shown in FIG. 10 is limited, which makes it difficult to obtain sufficient margin for supplying the external power supply voltage Vext.